How to generate a clock enable signal on FPGA

This post is about to tell you how to generate a clock enable signal (not gated clocks) to drive another logic using the same clock domain instead of creating another clock (using clock dividers or clock gating) possibly causing FPGA timing issues (as created by non-dedicated FPGA clock generators) or clock domain crossing problems such as metastability, data loss, and data incoherency if it is not taken care. 

It is recommended by both Xilinx and Altera to use clock enable, which can help save FPGA clock resources and improve FPGA timing characteristics and timing analysis of the design. 

The multi-clock domain crossing problem is very common in digital logic design. When you interface signals between different clock domains, metastability and data loss are likely to happen due to setup/hold time violations. Check HERE to understand what metastability is and why it occurs. The most popular way to prevent this is by using multi-Flip-Flop synchronizers to synchronize the input signals from another clock domain. 

To avoid the FPGA timing issues or clock domain crossing issues, it is recommended to generate a slow clock enable signal instead of creating another slower clock (using clock dividers or clock gating) to drive another logic part of your design. 

For example, in your FPGA, there is a 50MHz clock available, but you want to drive another part of your design using a slower clock of 1KHz. Instead of creating another clock of 1KHz, you should create a 1KHz clock enable signal. 

Below is an example VHDL code for generating the slow clock enable signal:

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects,
-- Generate clock enable signal instead of creating another clock domain
-- Assume that the input clock : clk_50MHz
signal clock_1KHz_enable  : std_logic;
signal counter : std_logic_vector(15 downto 0):=x"0000";
constant DIVISOR: std_logic_vector(15 downto 0):= x"C34F";
-- Generate the slow enable signal instead of creating another clock of 1KHz
-- 
process(clk_50MHz)
begin
  if(rising_edge(clk_50MHz)) then
    if(counter = DIVISOR) then
      counter <= x"0000";
      clock_1KHz_enable <= '1';
    else
      clock_1KHz_enable <= '0';
      counter <= counter + x"0001";
    end if;
  end if;
end process;
-- Use the same clock and the slow clock enable signal above 
-- to drive another part of the design to avoid domain crossing issues
process(clk_50MHz)
begin
  if(rising_edge(clk_50MHz)) then
    if(clock_1KHz_enable = '1') then
      -- Add your logic here
      -- It will be executed like a process of 1Khz clock
    end if;
  end if;
end process;

By creating the clock enable signal instead, all the logic in your design are driven by the same clock so that you won't need to worry about the FPGA timing issues or the multi-clock domain crossing problems. You can change the DIVISOR constant value to get any clock enable frequency that you want. Another Verilog example code for generating a slow clock enable signal instead of creating another clock domain: here.
Another VHDL example code here and Verilog example code here.

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