How to write Verilog Testbench for bidirectional/ inout ports

This post describes how to write a Verilog testbench for bidirectional or inout ports. This happens in special designs which contain bidirectional or inout ports such as I2C core, IO pads, memories, etc. 

In this post, I will give an example how to write testbench code for a digital IO pad. Basically, the IO pad has logic inputs DS, OEN, IE, PE to configure the IO pad as an input or output. When DS = OEN = IE = PE = 1, the IO pad operates as an input pad. Thus, the data from the bidirectional port PAD are written into the output C. When DS = PE =1 and OEN = IE = 0, the IO pad operates as an output pad. Therefore, the signal from the input I is passed to the bidirectional port PAD.

Block diagram of the Verilog testbench

As shown in the block diagram of the Verilog testbench, the IO pad under test is the DUT block.  Block 0 controls the inout port PAD as follows:

assign PAD = wr==1 ? din:1'bz;

When wr==1, the inout port PAD operates as an input, so PAD = din. When wr==0, the inout port PAD is assigned to a high impedance 1'bz. Thus, it becomes an output to get data from the input I of the IO pad.

Block 1 is the main testbench to generate test cases to check the input/ output functionality of the IO pad.

Below is the full Verilog testbench for the IO pad.

`timescale 1ns/10ps
// fpga4student.com
// FPGA projects, Verilog projects, VHDL projects
// How to write a verilog testbench for bidirectional/ inout port 
module test_IO();

reg DS,OEN,IE,PE,I,din;
wire PAD;
reg wr;
wire C;
// inout port
assign PAD = wr==1 ? din:1'bz;

DIGITAL_IO dut(I,DS,OEN,PAD,C,PE,IE);

initial begin
 // test the pad as an input
 wr=1;
 DS=1;
 OEN=1;
 din=0;
 IE=1;
 PE=1;
 #100;
 din=1;
 #100;
 din=0; 
 #100;
 din=1;
 #100;
 din=0;
 #100;
 din=1;
 #100;
 din=0;
 #100;
 din=1;
 #100;
 din=0; 
 #100;
 wr=0;
 // test the pad as an output
 // by reading data out 
 #1000;
 DS=1;
 OEN=0;
 din=0;
 IE=0;
 PE=1;
 I=1;
 #100;
 I=0; 
 #100; 
 I=1;
 #100;
 I=0; 
 #100;
 I=1;
 #100;
 I=0; 
 #100;
 end 

endmodule 

Simulation waveform for the bidirectional port:

The simulation waveform shows that when wr= DS = OEN = IE = PE = 1, the IO pad operates as an input pad and the signal from bidirectional port PAD is passed to the output C. When DS = PE =1 and OEN = IE = 0, wr=0 enables the IO pad operating as an output pad. Therefore, the signal from the bidirectional port PAD is read from the input port I.
In short, the takeaway stuff is the following 'assign' Verilog statement:

assign PAD = (wr==1) ? din:1'bz;

Recommended Verilog projects:

1. What is an FPGA? How Verilog works on FPGA

2. Verilog code for FIFO memory
3. Verilog code for 16-bit single-cycle MIPS processor
4. Programmable Digital Delay Timer in Verilog HDL
5. Verilog code for basic logic components in digital circuits
6. Verilog code for 32-bit Unsigned Divider
7. Verilog code for Fixed-Point Matrix Multiplication
8. Plate License Recognition in Verilog HDL
9. Verilog code for Carry-Look-Ahead Multiplier
10. Verilog code for a Microcontroller
11. Verilog code for 4x4 Multiplier
12. Verilog code for Car Parking System
13. Image processing on FPGA using Verilog HDL
14. How to load a text file into FPGA using Verilog HDL
15. Verilog code for Traffic Light Controller
16. Verilog code for Alarm Clock on FPGA
17. Verilog code for comparator design
18. Verilog code for D Flip Flop
19. Verilog code for Full Adder
20. Verilog code for counter with testbench
21. Verilog code for 16-bit RISC Processor
22. Verilog code for button debouncing on FPGA
23. How to write Verilog Testbench for bidirectional/ inout ports

24. Tic Tac Toe Game in Verilog and LogiSim
25. 32-bit 5-stage Pipelined MIPS Processor in Verilog (Part-1)
26. 32-bit 5-stage Pipelined MIPS Processor in Verilog (Part-2)
27. 32-bit 5-stage Pipelined MIPS Processor in Verilog (Part-3)

28. Verilog code for Decoder
29. Verilog code for Multiplexers
30.  N-bit Adder Design in Verilog
31. Verilog vs VHDL: Explain by Examples
32. Verilog code for Clock divider on FPGA
33. How to generate a clock enable signal in Verilog
34. Verilog code for PWM Generator
35. Verilog coding vs Software Programming