VHDL code for a 8-bit comparator is presented in this post. 74F521 is an 8-bit identity comparator which provides the low output if two 8-bit inputs are matched.
Below are the truth table and symbol of the comparator.
![VHDL code for comparator](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhjXS2N0kOeUzaq4DHLV55VtkC-Onn9SnQ4crsQzWuK_-t_GPI_hY7-NWYa04bwUYC1QWE-pj5_FQ76i2JTgII3l6A34DqIVvb8nWCv2wsfT91lLrP0GmChwaPkIONMAfzd-Uic2tWF63mw/s280/c3.png)
Truth table
![VHDL code for comparator](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEizC2pPvcJ69WKF_t1IZ6EFyRURiO-RTjj3hgIGxVLOg1BHtklMDHofwTF5sTUYVE9HrtaNTU5sxnDRV7O1x3Ao7UhDNy6GMg-9Mdc0y82f-OwrlnE_GzK9C9scNePWrsozs8T4XE1SHrJA/s400/c1.png)
Logic symbol of the comparator
![VHDL code for comparator](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh4X83rHy5DcP864WrsUD6zEGn2GZ2WPMkB5xJKG5g4ojyHrvAEY7U5mMiabCwf29b66DIYRXKLy7ovjdq5pFDjITH5E4DNc8Icb_TvACDRcvRoQJjNi_bDLK9s2VvNeU1tLS8ErWGUFk6Y/s280/c2.png)
Logic diagram (from datasheet of 74L521)
VHDL code for the comparator:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
-- VHDL project: VHDL code for comparator
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
entity comparator is
port (
clock: in std_logic;
-- clock for synchronization
A,B: in std_logic_vector(7 downto 0);
-- Two inputs
IAB: in std_logic; -- Expansion input ( Active low)
Output: out std_logic -- Output = 0 when A = B
);
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin
AB(0) <= (not A(0)) xnor (not B(0));
-- combinational circuit
AB(1) <= (not A(1)) xnor (not B(1));
AB(2) <= (not A(2)) xnor (not B(2));
AB(3) <= (not A(3)) xnor (not B(3));
AB(4) <= (not A(4)) xnor (not B(4));
AB(5) <= (not A(5)) xnor (not B(5));
AB(6) <= (not A(6)) xnor (not B(6));
AB(7) <= (not A(7)) xnor (not B(7));
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
process(clock)
begin
if(rising_edge(clock))then
if(AB = x"FF" and IAB = '0') then
-- check whether A = B and IAB =0 or not
Result <= '0';
else
Result <= '1';
end if;
end if;
end process;
Output <= Result;
end Behavioral;
Testbench VHDL code for the comparator:
-------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- fpga4student.com FPGA projects, Verilog projects, VHDL projects -- VHDL project: VHDL code for comparator ENTITY tb_comparator IS END tb_comparator; ARCHITECTURE behavior OF tb_comparator IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT comparator PORT( clock : IN std_logic; A : IN std_logic_vector(7 downto 0); B : IN std_logic_vector(7 downto 0); IAB : IN std_logic; Output : OUT std_logic ); END COMPONENT; --Inputs signal clock : std_logic := '0'; signal A : std_logic_vector(7 downto 0) := (others => '0'); signal B : std_logic_vector(7 downto 0) := (others => '0'); signal IAB : std_logic := '0'; --Outputs signal Output : std_logic; -- Clock period definitions constant clock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: comparator PORT MAP ( clock => clock, A => A, B => B, IAB => IAB, Output => Output ); -- Clock process definitions clock_process :process begin clock <= '0'; wait for clock_period/2; clock <= '1'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; A <= x"AA"; B <= x"BB"; wait for clock_period*10; B <= x"AA"; -- insert stimulus here wait; end process; -- fpga4student.com FPGA projects, Verilog projects, VHDL projects END;
Simulation waveform for the comparator:
![verilog/ VHDL code for 8-bit comparator](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgEBGxNyce1Ig7U4vYsSj78VVG4_-GH7EKh7PLNQyV97tKSlfrNqWQM0RTTOlI38sKo9mbzZnR6WYkVcKXGoQgBZxDfL_XVV1sqqpH6NVViYXmCHt0WSMfRvAh-f7Uk-ErCyqqpKVtxnfbq/s280/c5.png)
Recommended VHDL projects:
1. What is an FPGA? How VHDL works on FPGA
2. VHDL code for FIFO memory
3. VHDL code for FIR Filter
4. VHDL code for 8-bit Microcontroller
5. VHDL code for Matrix Multiplication
6. VHDL code for Switch Tail Ring Counter
7. VHDL code for digital alarm clock on FPGA
8. VHDL code for 8-bit Comparator
9. How to load a text file into FPGA using VHDL
10. VHDL code for D Flip Flop
11. VHDL code for Full Adder
12. PWM Generator in VHDL with Variable Duty Cycle
13. VHDL code for ALU
14. VHDL code for counters with testbench
15. VHDL code for 16-bit ALU
16. Shifter Design in VHDL
17. Non-linear Lookup Table Implementation in VHDL
18. Cryptographic Coprocessor Design in VHDL
1. What is an FPGA? How VHDL works on FPGA
2. VHDL code for FIFO memory
3. VHDL code for FIR Filter
4. VHDL code for 8-bit Microcontroller
5. VHDL code for Matrix Multiplication
6. VHDL code for Switch Tail Ring Counter
7. VHDL code for digital alarm clock on FPGA
8. VHDL code for 8-bit Comparator
9. How to load a text file into FPGA using VHDL
10. VHDL code for D Flip Flop
11. VHDL code for Full Adder
12. PWM Generator in VHDL with Variable Duty Cycle
13. VHDL code for ALU
14. VHDL code for counters with testbench
15. VHDL code for 16-bit ALU
16. Shifter Design in VHDL
17. Non-linear Lookup Table Implementation in VHDL
18. Cryptographic Coprocessor Design in VHDL
19. Verilog vs VHDL: Explain by Examples
20. VHDL Code for Clock Divider on FPGA
21. How to generate a clock enable signal instead of creating another clock domain
22. VHDL code for debouncing buttons on FPGA
23. VHDL code for Traffic light controller
24. VHDL code for a simple 2-bit comparator
25. VHDL code for a single-port RAM
26. Car Parking System in VHDL using FSM
27. VHDL coding vs Software Programming
20. VHDL Code for Clock Divider on FPGA
21. How to generate a clock enable signal instead of creating another clock domain
22. VHDL code for debouncing buttons on FPGA
23. VHDL code for Traffic light controller
24. VHDL code for a simple 2-bit comparator
25. VHDL code for a single-port RAM
26. Car Parking System in VHDL using FSM
27. VHDL coding vs Software Programming
No comments:
Post a Comment