How to load a text file or an image into FPGA

This FPGA tutorial presents two ways to load a text file or an image into FPGA using Verilog or VHDL for image processing. It can be really useful for functional verifications in real-time FPGA image processing projects.

The first way is to load a text file or an image into memory by reading the binary/hexadecimal file using Verilog/ VHDL code.

It is noted that Verilog/VHDL cannot read image file directly, but they can read binary text files. Therefore, the image is required to be converted into binary text files and then use Verilog/VHDL to read it. An image can be easily converted to hexadecimal/ binary data using Matlab, C, Python, etc.

For Verilog code, you can use $readmemh(for hexadecimal data) or $readmemb(for binary data) command to load a converted binary/hexadecimal text file directly. Example Verilog code for loading a text file or an image into FPGA using $readmemh: here. 

For VHDL code, the TEXTIO package provides necessary commands to read binary text files. Details of the VHDL tutorial on reading image/text file in VHDL can be found here. Another example VHDL code for loading a text file or an image into FPGA: here. 

The second way to load a text file or an image file into FPGA is to initialize it as the initial values of the block memory:

1. If you are using Altera FPGA, you can use Mega-Function in the MegaWizard Plug-In Manager in Quartus II to initialize a block memory with the text file or image-converted binary text file in the MIF format. A sample .mif file is here.

You can read more details the process how to use Megafunction in Altera as follows: User guide memory initialization

2. If you are using Xilinx FPGA, use the Core Generator in Xilinx ISE or IP core in Vivado to generate a block memory with the initial content as the text file or image-converted binary text files. The initial data file must be in .coe format. A sample .coe file is here.

You can read more details how to generate a block memory using CORE Generator in Xilinx ISE: Block memory Generator Xilinx

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