In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and random counter.
Verilog code for up counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for up counter module up_counter(input clk, reset, output[3:0] counter ); reg [3:0] counter_up; // up counter always @(posedge clk or posedge reset) begin if(reset) counter_up <= 4'd0; else counter_up <= counter_up + 4'd1; end assign counter = counter_up; endmodule
Verilog testbench code for up counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for up counter with testbench // Testbench Verilog code for up counter module upcounter_testbench(); reg clk, reset; wire [3:0] counter; up_counter dut(clk, reset, counter); initial begin clk=0; forever #5 clk=~clk; end initial begin reset=1; #20; reset=0; end endmodule
Simulation waveform for up counter:
Verilog code for down counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for down counter module down_counter(input clk, reset, output [3:0] counter ); reg [3:0] counter_down; // down counter always @(posedge clk or posedge reset) begin if(reset) counter_down <= 4'hf; else counter_down <= counter_down - 4'd1; end assign counter = counter_down; endmodule
Verilog testbench code for down counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for down counter with testbench // Testbench Verilog code for down counter module downcounter_testbench(); reg clk, reset; wire [3:0] counter; down_counter dut(clk, reset, counter); initial begin clk=0; forever #5 clk=~clk; end initial begin reset=1; #20; reset=0; end endmodule
Simulation waveform for down counter:
Verilog code for up-down counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for up-down counter module up_down_counter(input clk, reset,up_down, output[3:0] counter ); reg [3:0] counter_up_down; // down counter always @(posedge clk or posedge reset) begin if(reset) counter_up_down <= 4'h0; else if(~up_down) counter_up_down <= counter_up_down + 4'd1; else counter_up_down <= counter_up_down - 4'd1; end assign counter = counter_up_down; endmodule
Verilog testbench code for up-down counter:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for up-down counter with testbench // Testbench Verilog code for up-down counter module updowncounter_testbench(); reg clk, reset,up_down; wire [3:0] counter; up_down_counter dut(clk, reset,up_down, counter); initial begin clk=0; forever #5 clk=~clk; end initial begin reset=1; up_down=0; #20; reset=0; #200; up_down=1; end endmodule
Simulation waveform for up-down counter:
Verilog code for random counter using LFSR:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for random counter using linear shift feedback register module random_counter_lfsr(input clk, rst_n, input[4:0] initialized_value, output[4:0] counter_random); wire [4:0] counter_lfsr; wire d_xor; xor xor_u(d_xor,counter_lfsr[1],counter_lfsr[4]); D_FF u0(.q(counter_lfsr[0]), .d(counter_lfsr[4]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[0])); D_FF u1(.q(counter_lfsr[1]), .d(counter_lfsr[0]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[1])); D_FF u2(.q(counter_lfsr[2]), .d(d_xor), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[2])); D_FF u3(.q(counter_lfsr[3]), .d(counter_lfsr[2]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[3])); D_FF u4(.q(counter_lfsr[4]), .d(counter_lfsr[3]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[4])); assign counter_random = counter_lfsr; endmodule // FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for random counter using linear shift feedback register // Verilog code for D_FF using in random counter module D_FF (q, d, rst_n, clk,init_value); output q; input d, rst_n, clk,init_value; reg q; always @(posedge clk or negedge rst_n) if (~rst_n) q <= init_value; else q <= d; endmodule
Verilog testbench code for random counter using LFSR:
// FPGA projects using Verilog/ VHDL // fpga4student.com: FPGA projects, Verilog projects, VHDL projects // Verilog code for random counter with testbench // Testbench Verilog code for random counter module randomcounter_testbench(); reg clk, reset; reg [4:0] initialized_value; wire [4:0] counter_random; random_counter_lfsr dut( clk, reset, initialized_value, counter_random); initial begin clk=0; forever #5 clk=~clk; end initial begin reset=0; initialized_value=5'b11111; #20; reset=1; end endmodule
Simulation waveform for random counter:
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