VHDL code for FIFO Memory

As requested by some readers, I made the VHDL code for the FIFO memory in this VHDL project(Verilog code for FIFO memory). 

The FIFO has 16 8-bit data-width stages and five status signals including overflow, underflow, empty, full and threshold. The VHDL code for the FIFO memory is verified by the same Verilog testbench code by doing a mixed language simulation on Xilinx ISIM. 

Verilog code for FIFO memory

In this project, Verilog code for FIFO memory is presented. The First-In-First-Out (FIFO) memory with the following specification is implemented in Verilog:

• 16 stages
• 8-bit data width 
• Status signals: 
• Full: high when FIFO is full else low.
• Empty: high when FIFO is empty else low.
• Overflow: high when FIFO is full and still writing data into FIFO, else low.
• Underflow: high when FIFO is empty and still reading data from FIFO, else low.
• Threshold: high when the number of data in FIFO is less than a specific threshold, else low.

Verilog code for 16-bit single cycle MIPS processor

In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor, which is widely used by many universities in academic courses related to computer organization and architecture. 

The Instruction Format and Instruction Set Architecture for the 16-bit single-cycle MIPS are as follows:

Instruction set for the MIPS processor

Delay timer (LS7212) in Verilog HDL

Today's project is an implementation of a programmable digital delay timer in Verilog HDL. Verilog code for the delay timer is fully presented.

Basic digital logic components in Verilog HDL

In this Verilog project, basic blocks in digital logic design such as D-Flip-Flop, adders, ALU, registers, memory, multiplexers, decoders, counters, etc.  are implemented in Verilog HDL for beginners.

A low pass FIR filter for ECG Denoising in VHDL

In this VHDL project, a simple low pass FIR filter is implemented in VHDL for ECG Denoising. VHDL code for the FIR filter is fully presented. 

The VHDL code for the FIR filter is simulated and verified by comparing the simulated results in Modelsim with the correct results generated from Matlab. Sample ECG inputs are provided in input.txt files, the VHDL filter code reads those ECG files, apply digital filtering, and write the results into output.txt files for verification.